Computer for use with ring laser rotational rate sensors

ABSTRACT

A computer responsive to the pulse sequence output signal of a ring laser rotational rate sensor having contra-rotating beams and biasing means to prevent mode locking. The biasing means selectively changes the effective optical path length around the ring of one of the beams with respect to the other. The pulse repetition frequency of the laser output pulse sequence is representative of the difference in oscillation frequency between the contra-rotating beams. The computer comprises a bias control circuit for selecting the polarity of the bias applied to the ring and includes a compensation circuit for providing a bias compensation pulse sequence whose pulse repetition frequency is representative of the magnitude of the applied bias. The computer in addition provides signals representative of the polarities of the laser output pulse sequence and the bias compensation pulse sequence respectively. The laser polarity is chosen in accordance with the selected polarity of the applied bias. The polarity of the bias compensation pulse sequence is chosen opposite to the selected laser polarity. A pulse sequence combining circuit is included for combining the laser output pulse sequence and the bias compensation pulse sequence thereby providing a combined pulse sequence. The pulse sequence combining circuit furthermore combines the associated polarity signals thereby providing a combined polarity signal. The combined pulse sequence is integrated in accordance with the combined polarity signal for providing a signal representative of the ring about an axis normal thereto.

United States Patent [191 Dendy et al. 7

Feb. 6, 1973 COMPUTER FOR USE WITH RING LASER ROTATIONAL RATE SENSORS[75] Inventors: Joe B. Dendy, Phoenix, Ariz.; Kenneth Thomson, LloydNeck; Robert F. Morrison, l-lalesite, both of NY.

[73] Assignee: Sperry Rand Corporation [22] Filed: March 19, 1970 [21]Appl. No.: 20,965

[52] U.S. Cl. ..235/l50.31, 235/150.3, 235/156, 356/106 LR [51] Int. Cl"G06f 15/20, G01b 9/02 [58] Field of Seareh.235/183, 150.25, 150.3,150.31; 356/106 LR [56] References Cited UNITED STATES PATENTS 3,373,6503/1968 Killpatrick ..356/106 LR 3,392,622 7/1968 Senf ..356/106 LR3,512,890 5/1970 McLaughlin .....356/l06 LR 3,597,088 8/1971 Catherin..356/1 06 LR Primary ExaminerFelix D. Gruber Attorney-S. C. Yeatonsignal of a ring laser rotational rate sensor having contra-rotatingbeams and biasing means to prevent mode locking. The biasing meansselectively changes the effective optical path length around the ring ofone of the beams with respect to the other. The pulse repetitionfrequency of the laser output pulse sequence is representative of thedifference in oscillation frequency between the contra-rotating beams.The computer comprises a bias control circuit for selecting the polarityof the bias applied to the ring and includes a compensation circuit forproviding a bias compensation pulse sequence whose pulse repetitionfrequency is representative of the magnitude of the applied bias. Thecomputer in addition provides signals representative of the polaritiesof the laser output pulse sequence and the bias compensation pulsesequence respectively. The laser polarity is chosen in accordance withthe selected polarity of the applied bias. The polarity of the biascompensation pulse sequence is chosen opposite to the selected laserpolarity. A pulse sequence combining circuit is included for combiningthe laser output pulse sequence and the bias compensation pulse sequencethereby providing a combined pulse sequence. The pulse sequencecombining circuit furthermore combines the associated polarity signalsthereby providing a combined polarity signal. The combined pulsesequence is integrated in accordance with the combined polarity signalfor providing a signal representative of the ring about an axis normal57 thereto.

A computer responsive to the pulse sequence output ABSTRACT 22 Claims, 7Drawing Figures LASER PULSE SYNCHRONIZER 2O 1 FROM 25 f +VOLTS oc oc s QA PULSES S Q SYNCHRONIZED LASER LASER PULSE PULSE SEQUENCE u 4 RINGSEQUENCE l l L LASER c r 5 :5 CLEAR \23 l J OPTICAL 27 ems 29 b -B|AS IPOLARITY OF LASER L 28 PULSE SEQUENCE 26 mgr-:5 POLARITY s EgEcToR lBIAS OFF a l BIAS 0N V l 62 l l BIAS s a 30x T2 T 63 FROM43 'j E|AS R QI 65 4 EHA CONTROL I C q iiji L PATENTEDFEB 6 I975 SHEET 10F 6 OUTPUTPULSE RATE (PULSES/SEC.)

PO$ I TI VE OPTICAL BIAS (6 DEG/SEC.) SLOPE lz s'Eb/PuLsE)" DEG. /SEC.

I ccw ANGULAR RATE cw ANGULAR RATE (DEG. /SEC.) (DEG. /SEC.)

NEGATIVE OPTICAL BIAS INSTRUMENT BIAS (TYP. .003 DEG/SEC.)

F|G.l.

BYl-POBERT F MORE/SON PATENTEDFEB 6 I973 SHEET 8 OF 6 LASER PULSESEQUENCE O.l MHZ CLOCK PULSES Ill- 111m}! .IIHH

- I PULSE/8 SECS SYNCHRONIZED LASER PULSE SEQUENCE 3|.25 KHZ INTERVAL lINTERVAL 2 INVENTORS JOE B BEND) KENNETH THOMSON B5OBERT F. MORE/SONATTORNEY COMPUTER FOR USE WITH RING LASER ROTATION AL RATE SENSORSBACKGROUND OF THE INVENTION 1. Field of the Invention The presentinvention relates to ring laser rotational rate sensor systems.

2. Description of the Prior Art Prior art ring laser rotational ratesensor systems measure the magnitude of the angular rotation of the ringabout an axis normal thereto by combining portions of thecontra-rotating beams of the ring laser on the photosensitive surface ofa photodetector and measuring the beat frequency resulting therefrom. Aknown technique for determining the sense of the rotation of the ring isto utilize a second photodetector comparing the phase relationshipbetween the beat frequency signal therefrom and the beat frequencysignal from the first photodetector. The use of a second photodetectorincreases the undesired backscattering phenomenon with respect toa-single photodetector configuration thereby increasing the mode lockingthreshold of the ring laser.

Ring laser configurations are known utilizing a single photodetector inthe combining optics associated therewith, wherein the direction ofrotation is determined by complex bias switching procedures andcomputations. I

SUMMARY OF THE INVENTION The present invention comprises a computerresponsive to the pulse sequence output signal of a ring laserrotational rate sensor having contra-rotating beams and biasing meansfor selectively changing the effective optical path length around thering of one of the beams with respect to the other. The pulse repetitionfrequency of the laser output pulse sequence is representative of thedifference in oscillation frequency between the contra-rotating beams. I

The computer determines the magnitude and sense of the rate of rotationof the ring about an axis normal thereto from the signal provided by asingle photodetector in the combining optics of the laser. The computerprovides unique polarity selection means for determining the sense ofrotation of the ring.

The computer comprises a bias control circuit for selecting the polarityof the bias applied to the ring and includes a compensation circuit forproviding a bias compensation pulse sequence whose pulse repetitionfrequency is representative of the magnitude of the applied bias. Thecomputer in addition provides signals representative of the polaritiesof the laser output pulse sequence and the bias compensation pulsesequence respectively. The laser polarity is chosen in accordance withthe selected polarity of the applied bias. The polarity of the biascompensation pulse sequence is chosen opposite to the selected laserpolarity. A pulse sequence combining circuit is included for combiningthe laser output pulse sequence and the bias compensation pulse sequencethereby providing a combined pulse sequence. The pulse sequencecombining circuit furthermore combines the associated polarity signalsthereby providing a combined polarity signal. The combined pulsesequence is integrated in accordance with the combined polarity signalfor providing a signal representative of the rate and direction ofrotation of I the ring about an axis normal thereto.

The bias may be applied at low rates of rotation of the ring to preventmode locking and the bias polarity may be periodically alternated tominimize long-term drift errors.

BRIEF DESCRIPTION OF THE DRAWINGS DESCRIPTION OF THE PREFERREDEMBODIMENT Referring to FIG. 1, the input-output characteristic of atypical ring laser is illustrated. Abscissa axis 10 represents theangular rate of rotation of the ring about an axis normal thereto. Thesection of the abscissa axis 10 to the right of the origin isrepresentative of clockwise rotation and the section thereof to the leftof the origin is representative of counterclockwise rotation. Clockwiserotation may be designated as having a positive polarity andcounterclockwise rotation may be designated as having a negativepolarity.

Ordinate axis 11 represents the frequency of the laser output pulsesequence, which frequency is representative of the rotational rate ofthe ring. The section of the ordinate axis 11 above the origin isrepresentative of positive frequencies and the section of the axis 11below the origin is representative of negative frequencies. It will beappreciated that negative frequencies do not have physical significancebut that the polarity of the frequency is a designation applied by thecomputer of the present invention to the laser output pulse sequence soas to determine the sense of rotation of the ring, in a manner to beexplained.

Ideally, the input-output characteristic of a ring laser should be alinear curve intersecting the origin. The input-output characteristicillustrated in FIG. 1, however, exhibits non-linear properties on bothsides of the origin. It is understood that these non-linearities arecaused by the well-known mode-locking characteristic of ring lasers atlow rates of rotation of the ring. The present invention provides biaspolarity selection techniques utilized in conjunction with biasingprocedures for negating the effect of the mode-locking phenomenon andfor providing an accurate indication of the rate of rotation and thesense thereof of the ring at low rotation rates, in a manner'to beexplained.

Ideally, a linear extension of the linear portions of the input-outputcharacteristic of a ring laser should intersect the origin. However, thelinear extension illustrated in FIG. 1 by the dashed line is offset fromthe origin. This offset is caused by asymmetries inherent in practicalring laser configurations. Means are provided by the present inventionto negate the effect of these asymmetries, in a manner to be explained.

Referring now to FIG. 2, a conventional ring laser 20 is illustratedincluding optical biasing apparatus 21 which selectively changes theeffective optical path length of one of the laser beams with respect tothe other for the purpose of preventing mode-locking. The opticalbiasing apparatus 21 may, for example, comprise a conventional Faradaybiasing cell. Such an arrangement may be exemplified by the devices ofUS. Pat. No. 3,373,650 Laser Angular Rate Sensor by J.E. Killpatrickissued Mar. 19, 1968 or US. Pat. No. 3,392,622 Electromagnetic RotationSensor by H. R. Senf, issued July 16, I968. The ring laser 20 may bemounted to the body of a vehicle for navigational purposes. Theringlaser 20 provides a laser output pulse sequence generally to a laserpulse synchronizer 22.

The output pulses from the laser 20 occur asynchronously with respect tothe clock pulses of the computer of the present invention. The laserpulse synchronizer 22 provides pulses, in a manner to be explained,which occur synchronously with respect to the computer clock pulses andcorrespond in a one-to-one manner to the asynchronous laserpulses.

The laser pulse synchronizer 22 includes a flip flop 23 having a triggerinput to which the pulse sequence from the laser 20 is applied. A binaryONE signal is applied to the set input of the flip flop 23 which signalmay be represented by a positive voltage as indicated by the legend. Abinary ZERO signal is applied to the reset input of the flip flop 23which signal may be represented by ground potential. With theseconnections, the flip flop 23 is set to the Q state in response to thefalling edge gt a pulse applied to its trigger input. The Q and the Qoutputs of the flip flop 23 are connected respectively to the set andthe reset input of a flip flop 24. Clock pulses from a conventionalclock pulse source 25 are applied to the trigger input of the flip flop24. With these COllllCCtiOl'lS, the flip flop 24 is set to the Q stateor the Q state in response to the falling edge of a clock pulse appliedto its trigger input when the flip flop 2 3 is in the Q state or in theQ state respectively. The Q output of the flip flop 24 is connected tothe clear input of the flip flop 23 whereby the flip flop 23 will bereset to the Q state whenever the flip flop 24 is set to its Q state.The Q output of the flip flop 24 provides a laser pulse sequencesynchronized with respect to the clock pulses of the computer in amanner to be explained.

A laser polarity selector circuit 26 is included in the computer of thepresent invention for providing a signalrepresentative of the polarityof the laser pulse sequence. The laser polarity selector circuit 26 iscomprised of AND gates 27 and 28 and an-OR gate 29. The inputs to theAND gate 27 receive signals from a bias control circuit 30. The AND gate28 is also responsive to the bias control circuit 30 and in additionreceives an input from a rate detector circuit 31. The outputs of theAND gates 27 and 28 are applied as inputs to the OR gate 29. The OR gate29 provides the signal representative of the polarity of the laser pulsesequence for reasons and in a manner to be explained.

Bias compensation and polarity selection circuits 36 are included in thecomputer of the present invention for providing a bias compensationpulse sequence on conductor 37 whose pulse repetition frequency isrepresentative of the magnitude of the optical bias applied to the ringlaser 20'by the optical biasing apparatus 21. The bias compensation andpolarity selection circuits 36 comprise apparatus of the digitaldifferential analyzer type wherein Y-registers 38, 39 and 40selectivelyprovide predetermined binary numbers to an arithmetic unit451,-in a conventional manner, for

selective accumulation in an R-register 47, thereby selectivelyproviding an instrument compensation pulse sequence, a positive biascompensation pulse sequence or a negative bias compensation pulsesequence, respectively, on conductor 37 in a manner to be explained.

The bias compensation and polarity selection circuits 36 compriseinstrument bias Y-register 38 which stores a predetermined binary numberrepresentative of the magnitude of the zero offset of the laserinput-output characteristic as previously described with respect toFIG. 1. The register 38 provides the binary number stored therein as aninput to an AND gate 42. A conventional timing signal generator 43,which receives clock pulses from the clock pulse source 25, provides aninterval 2 signal, illustrated in FIG. 3, as an input to the AND gate42.

A positive bias Y-register 39, which stores a predetermined binarynumber representative of the magnitude of the positive optical biasapplied to the ring laser 20 by the optical bias-apparatus 21, providesthe binary number as an input to an AND gate 44. The AND gate 44 inaddition receives an interval 1 signal, illustrated in FIG. 3, from thetiming signal generator 43. The AND gate 44 also receives signals fromthe bias control circuit 30 in a manner to be described.

A negative bias Y-register 40, which stores a predetermined binarynumber representative of the magnitude of the negative optical biasapplied to the ring laser 20 by the optical bias apparatus 21, providesthe binary number as an input to an AND'gate 45. The AND gate 45inaddition receives the interval 1 signal in a manner similar to thatdescribed with respect to the AND'gate' 44. The AND gate 45 alsoreceives signals from the bias control circuit 30 in a manner to bedescribed.

The AND gates 42, 44 and 45 provide input signals to an OR gate 46. Thesignal provided by the OR gate 46 to the Y-input of the arithmetic unit41 is selectively representative of the binary numbers stored in the Y-registers 38, 39 and 40 in accordance with the timing signals providedby the timing signal generator 43 and the bias control signals providedby the bias control circuit 30.

The arithmetic unit 41 and an R-register47 comprise a circuit of theconventional digital differential analyzer type commonly sharing theY-registers 38, 39 and 40. The dx input to the arithmetic unit 41 isprovided from a source of positive voltage which is representative of abinary ONE signal for reasons to be explained.

The apparatus 36 includes polarity selection circuits comprising aninstrument bias polarity selection switch 52 with associated sources ofpotential indicated by the legend, AND gates 53 and 54, an OR gate 55,as well as the circuits included in the arithmetic unit 41 for providinga compensation polarity signal on a conductor 56 in a manner to beexplained.

The AND gate 53 receives as inputs a signal from the bias controlcircuit 30 and the interval 1 signal from the timing signal generator43. The AND gate 53 provides a signal representative of the oppositepolarityto that of the optical bias applied by the optical biasapparatus 21' to the ring laser 20, in a manner to be described.

The AND gate 54 receives a signal from the switch 52 as well as theinterval 2 signal from the timing signal generator 43. The AND gate 54provides a signal representative of the polarity of the instrument biasselected by the switch 52 in a manner to be described.

The AND gates 53 and 54 provide input signals to an OR gate 55 which inturn providesa signal to the sx input of the arithmetic unit 41. Thesignal provided to the sx input of the arithmetic unit 41 is selectivelyrepresentative of the polarity of the instrument bias or of a polarityopposite to that of the applied optical bias in accordance with the biascontrol signals provided by the bias control circuit 30 and the timingsignals provided by the timing signal generator 43 in a manner to beexplained.

The arithmetic unit 41, in turn, provides the compensation polaritysignal on the conductor 56 in a manner to be described.

As previously explained, the optical bias apparatus 21, the laserpolarity selector 26 and the bias compensation and polarity selectioncircuits 36 receive bias control signals from the bias control circuit30. The bias control circuit 30 generally receives an input signal fromthe rate detector 31. The signal from the rate detector 31 is applied asinputs to AND gates 62 and 63 via an inverter 64. The AND gates 62 and63 provide the bias control signals previously mentioned in a manner tobe described.

The AND gates 62 and 63 also receive inputs from the Q and O outputsrespectively of a flip flop 65. The Q and the O outputs of the flip flop65 are also connected, respectively, to the reset and the set inputthereof. With these connections the flip flop 65 toggles in response topulses applied to the trigger input thereof. The trigger input to theflip flop 65 is responsive to the timing signal T,, as illustrated inFIG. 3 from the timing signal generator 43.

The laser pulse sequence provided by the laser pulse synchronizer 22,the polarity signal provided by the provided via an inverter 70 by thepolarity signal from the laser polarity selector 26 and a fourth inputis provided thereto via an inverter 71 by the compensation polaritysignal appearing on the conductor 56. The AND gate 69 provides a signalwhenever a positive laser pulse and a positive bias compensation pulseoccur simultaneously with respect to each other, in a manner to beexplained.

An AND gate 72 receives an input signal from the laser pulse sequenceprovided by the laser pulse synchronizer 22. A second input to the ANDgate 72 is provided by the bias compensation pulses appearing on theconductor 37. The third and fourth inputs to the AND gate 72 areprovided respectively by the polarity signal from the laser polarityselector 26 and the compensation polarity signal appearing on theconductor 56. The AND gate 72 provides a signal whenever a negativelaser pulse and a negative bias compensation pulse occur simultaneouslywith respect to each other, in a manner to be described.

The AND gates 69 and 72 provide inputs to an OR gate 73. The OR gate 73,in turn, provides a signal to an OR gate 74 whose output is theconductor 67 previously discussed. Whenever laser and bias compensationpulses having the same associated polarity with respect to each other,occur simultaneously with respect to each other, a pulse is provided onthe conductor 67 in a manner to be described.

The AND gate 72 also provides a signal to an OR gate 91 thus providing asignal on the conductor 68 via laser polarity selector 26, the biascompensation pulse sequence appearing on the conductor 37 and thecompensation polarity signal appearing on the conductor 56 are appliedgenerally as inputs to a pulse sequence combining circuit 66. The pulsesequence combining circuit 66 provides a pulse on a conductor 67 foreach singly occurring laser pulse or bias compensation pulse 1 andprovides the polarity signal associated therewith on a conductor 68.Laser and bias compensation pulses that occur simultaneously withrespect to eachother and have opposite associated polarities withrespect to each other are cancelled by the pulse sequence combiningcircuit 66. When a laser pulse and a bias compensation pulse occursimultaneously with respect to each other but have the same associatedpolarity with respect to each other, one of the pulses is transmitted tothe conductor 67 with the associated polarity signal appearing onconductor 68, and the other pulse with the associated polarity signal isstored for transmission thereafter in a manner to be explained.

The pulse sequence combining circuit 66 includes an AND gate 69 whichreceives the laser pulse sequence provided by the laser pulsesynchronizer 22 as an input signal. A second input signal is provided tothe AND gate 69 by the bias compensation pulses appearing on theconductor 37. A third input to the AND gate 69 is an AND gate 92 and anOR gate 85 which signal is representative of the polarity of the pulseprovided on the conductor 67, in a manner to be explained. The output ofthe OR gate 73 in addition provides an inhibiting signal via an inverterto AND gates 75 and 76 for reasons to be discussed.

The outputs from the AND gates 69 and 72 are combined in an OR gate 77which provides a signal to the set input of a slip flop 78. The flipflop 78 is utilized to store one pulse of each pair of laser and biascompensation pulses occurring simultaneously with respect to each otherhaving the same polarity with respect to each other and for transmittingthe stored pulse via the AND gate 75 and the OR gate 74 to the conductor67 after the other pulse of the pair has been transmitted thereon in amanner to be explained.

The output of the AND gate 75 is connected to the reset input of theflip flop, 78 for resetting the flip flop 78 after the pulse storedtherein has been transmitted through the AND gate 75. The pulses of thewaveform t as illustrated in FIG. 3, are applied from the timing signalgenerator 43 to the trigger of the flip flop 78 for entering thereintothe binary conditions appearing at the set and resetinputs thereof.

The outputs of the AND gates 69 and 72 are applied 3 respectively to theset and reset inputs of a flip flop 79. The pulses of the waveform tprovided by the timing signal generator 43 are applied to the triggerinput of the flip flop 79 thereby to store a positive polarity or anegative polarity in accordance with the polarity of the simultaneouslyoccurring laser and bias compensation pulses in a manner to beexplained. The Q output of the flip flop 79 provides a signalrepresentative of the stored polarity to the conductor 68 via the ANDgate 76 and the OR gate in a manner to be explained.

The laser pulses are applied directly as an input to an AND gate 86 andvia an inverter 87 as an input to an AND gate 88. Similarly, the biascompensation pulses are applied directly as an input to the AND gate 88and via an inverter 89 as an input to the AND gate 86. The AND gate 86provides a signal representative of a singly occurring laser pulse andthe AND gate 88 provides a signal representative of a singly occurringbias compensation pulse. The outputs of the AND gates 86 and 88 areapplied as inputs to the OR gate 73 which in turn provides a signal tothe conductor 67 via the OR gate 74 in a manner and for reasons to beexplained.

The output signal from the AND gate 86 and the polarity signal providedby the laser polarity selector 26 provide inputs to an AND gate 90.Similarly, the output signal from the AND gate 88 and the compensationpolarity signal provided on the conductor 56 provide inputs to an ANDgate 98. The AND gates 90 and 98 provide input signals to the OR gate 91which also receives an input signal from the AND gate 72. The OR gate91" provides an input signal to the AND gate 92 which also receives aninput signal from, the OR gate 73. The output of the AND gate 92 is inturn connected as an input to the OR gate 85. The AND gates 90, 92 and98 and the OR gates 85 and 91 provide a signal to the conductor 68 whichis representative of the polarity of ,the singly occurring laser andbias pulses applied to the pulse sequence combining circuits 66 in amanner to be explained.

The signals appearing on the conductor 67 are representative of acombined pulse sequence obtained from the laser pulse sequence providedby the laser pulse synchronizer 22 and the bias compensation pulsesequence provided by the bias compensation and polarity selectioncircuits 36.. The signal appearing on the conductor 68 is a combinedpolarity signal representative of the polarity associated with thepulses appearing on the conductor 67.

The combined pulse sequence appearing on the conductor 67 and thecombined polarity signal appearing on the conductor 68 are appliedrespectively to the dx and the sx inputs-of a scaling integrator 93. Thescaling integrator 93 may be a conventional digital differential signalapplied thereto. The counter 95 may be a conventional reversible counterproviding a binary digital output signal representative of the number ofpulses ap' plied to its input from the AND gate 96. The counterconveniently may be conditioned to count up by a binary ZERO signalapplied to its up-down control input 107 and may similarly beconditioned to count down by a binary ONE signal applied thereto. Thecounter may be reset to an initial condition, such as zero, by a signalapplied to a reset input 102. For reasons to be explained, the resettingof the counter 95 may be slightly delayed, by conventional means notshown, in response to the signal on the resetting input 102.

analyzer circuitof the type described in Design Of A One MegacycleIteration Rate DDA, Proceedings 1962 Spring Joint Computer Conference,AFIPS, Vol. 21, pp. 353-364, Bradley, R. E., and-Genna, J. F. Anadditional reference may be found in Real Time Digital DifferentialAnalyzer (DART), Proceedings 1954 Western Joint Computer Conference, pp.134-139, Meissner, L. P.

The scaling factor selected for the Y-register of the integrator 93 ischosen so that the pulses applied to a following sine-cosine computationcircuit 94 may be utilized directly thereby without requiring furtherscaling in the integrators associated therewith.

The dz and sz outputs of the scaling integrator 93 are applied generallyas inputs-to the rate detector 31. The rate detector 31 provides asignal on a conductor 97 to the bias control circuit 30 whenever themagnitude of the rate of rotation of the ring laser equals or exceeds apredetermined value. The dz output of the scaling integrator 93 isprovided to a reversible counter 95 via an AND gate 96.- The up-downcontrol of the counter 95 is provided by an ,up-down control input 107via a binary The inputs to an AND gate 103 are connected topredetermined output terminals of the reversible counter therebyproviding a signal whenever the reversible counter 95 attains apredetermined count. The output of the AND gate 103 is connecteddirectly to the set input of a flip flop 104 and through an inverter 105to the reset input thereof. The T signal, illustrated in FIG. 3, fromthe timing signal generator 43, is applied to the trigger input of theflip flop 104 for inserting the binary condition provided by the ANDgate 103 into the flip flop 104 in a manner to be-described. The Tsignal is also applied as the resetting signal to the reset terminal 102of the reversible counter 95. The Q output of the flip flop 104 providesa signal on the conductor 97 to the bias control circuit 30 whenever thereversible counter 95 attains the aforementioned predetermined count.The reversible counter 95 attains the predetermined count whenever therate of rotation of the ring laser equals or exceeds a predeterminedmagnitude.

The output of the AND gate 103 is also connected as an inhibiting inputto the AND gate 96 via an inverter 106 for reasons to be explained.

The inputs to an AND gate are connected to the output terminals of thereversible counter 95, in a conventional configuration, whereby the ANDgate 130 provides a signal whenever the reversible counter 95 attains acount of zero. An additional enabling input to the AND gate 130 isprovided by the Q output of the flip flop 104, for reasons to beexplained.

The output of the AND gate 130 provides input signals to AND gates 131and 132. The AND gate 131 also receives an input signal from the szoutput of the scaling integrator 93 and the AND gate 132 similarlyreceives an input signal, via an inverter 133, from the sz outputthereof. The AND gates 131 and 132 in turn provide signals to the setand reset inputs of a flip flop 108 respectively. The pulses from theAND gate 96 i provide the triggering signals to the trigger input of theflip flop 108. In a manner to be described, the flip flop 108 stores thepolarity signal associated with the pulse provided by the AND gate 96 tothe reversible counter 95 that caused the counter 95 to attain theaforementioned predetermined count. The Q output from the flip flop 108provides the laser polarity signal to the laser polarity selector 26 ina manner to be explained whenever the rate of rotation of the ring laserequals or exceeds the predetermined magnitude.

The Q and the Q outputs of the flip flop 108 provide input signals toAND gates 134 and 135 respectively. The AND gate 135 also receives aninput signal from the sz output of the scaling integrator 93 and the ANDgate 134 receives the inverse thereof via an inverter 136. The outputsof the AND gates 134 and 135 provide input signals to an OR gate 137.The OR gate 137 provides the aforementioned binary up-down controlsignal on the conductor 107 to the reversible counter 95.

The gates 134, 135, 136 and 137 are so arranged that the reversiblecounter 95 is not permitted to count down through zero. Whenever thecounter 95 attains a count of zero, the gates 134 through 137 provide acount up binary ZERO command on the conductor 107. The gates 134 through137 and the counter 95 are arranged in this manner so that theaforementioned predetermined count may represent the same magnitude ofthe rate of rotation of the ring 20 irrespective of the sense ofrotation thereof. Thus, the AND gate 103 may be responsive to thisaforementioned predetermined count to detect when the rate of rotationof the ring equals or exceeds the aforementioned predetermined magnitudefor both positive and negative directions of rotation of the ring 20 ina manner to be discussed.

As well as providing inputs to the rate detector circuit 31, the scalingintegrator 93 provides input signals generally to the sine-cosinecomputation circuit 94. The sine-cosine computation circuit 94 maybecomprised of conventional integrators of the digital differentialanalyzer type such as have previously been referenced with respect tothe DDA 93. The integrators 110 and 111 may be connected in aconventional manner to provide signals representative of "the sine andthe cosine of the input signals applied thereto. The dz and sz outputsprovided by the scaling integrator 93 are applied respectively inparallel to the dx and sx in puts to the integrators 110 and 111. The dzand sz outputs of the integrator l 11 are connected respectively to thedy and Sy inputs of the integrator 110. Similarly the dz output of theintegrator 110 is connected to the dy input of the integrator 111whereas the sz output of the integrator 110 is connected to the Sy inputof the integrator 111 via an inverter 112. With the connectionsdescribed, the integrators 110 and 111 provide the sine and thecosinerespectively of the input signals applied thereto in aconventional manner. v

The dz and sz output signals from the scaling integrator 93 are providedgenerally as inputs to a rate computation circuit 113. The ratecomputation circuit 113 converts the scaled laser pulse rate to a binarynumber representative of the sense and magnitude of the rate of rotationof the ring laser 20. The rate computation circuit 113 is comprised of aconventional integrator 114 of the digital differential analyzer typepreviously referenced and a pulse sequence combining circuit 115 whichmay be identical to the circuit 66 which has been previously described.The binary number representing rate of rotation of the laser is storedin the Y-register of the DDA integrator 114.

The laser pulse rate which is representative of the laser rate ofrotation is converted to a binary number representative of the laserrate of rotation in the following manner. The dx and sx inputs to theintegrator 1 14 are wired to volts and ground, respectively, which arerepresentative, respectively, of binary ONE and binary ZERO. This causesthe integrator to integrate with respect to time, and the output pulserate dz to be proportional to the number stored in the Y-register, thepolarity sz being the same as that of the number in the Y-register. Thispulse rate is subtracted from the laser pulse rate provided by thescaling DDA 93 in the pulse sequence combining circuit 115. Thedifference pulse rate is coupled to the dy input of integrator 114 andis integrated into the Y-register. Under steady state conditions, thedifference pulse rate will be zero and the integrator output pulse ratewillbe equal to the input pulse rate from the scaling DDA 93. Hence, thebinary number in the Y-register of the integrator is proportional to thelaser pulse rate from the scaling integrator 93, and is thusrepresentative of the magnitude and sense of the ring laser rate ofrotation.

In operation the ring laser 20 provides the laser pulse sequence, asillustrated in FIG. 3, to the laser pulse synchronizer 22. The pulsesfrom the ring laser 20 may result from either mechanical rotation of thering about an axis normal thereto or from optical bias provided by meansof the optical bias apparatus 21 or from a combination of the two. Laserpulses may additionally be provided by reason of the instrument zerooffset. The falling edge of each pulse of the laser pulse sequencetriggers the flip flop 23 to the 0 state as illustrated by waveform Aand the laser pulse sequence waveform of FIG. 3. The falling edge of thenext occurring clock pulse from the clock pulse source 25 consequentlytriggers the flip flop 24 to the Q state. The O output of the flip flop24 then clears the flip flop 23 to the O state as illustrated by thewaveform A, the clock pulse waveform and the synchronized laser pulsesequence waveform of FIG. 3. The falling edge of the next occurringclock pulse then resets the flip flop 24 back to the O state therebyproviding a pulse corresponding to the pulse from the ring laser 20 butsynchronized with the computer clock pulse source 25 as illustrated bythe synchronized laser pulse sequence waveform of FIG. 3.

Components of the laser pulse synchronizer 22 are now conditioned toreceive the next occurring pulse from the ring laser 20.

The bias control circuit 30 provides control signals to variouscomponents of the computer of the present invention: in response toasignal on the conductor 97 from the rate detector 31. This signal isrepresentative of the condition whereby the rate of rotation of the ringis equal to or greater than a predetermined rate. The manner in whichthe signal on the conductor 97 is generated will be explained later withrespect to the operation of the rate detector 31. Whenever the rate ofrotation of the ring is equal to or greater than the predetermined rate,the signal on the conductor 97 assumes the binary ONE state and wheneverthe rate of rotation of the ring is less than the predetermined rate,the signal on the conductor 97 assumes the binary ZERO state. Therefore,when the rate of rotation of the ring is less than the predeterminedrate, the inverter 64 of the bias control circuit 30 provides anenabling signal to the AND gates 62 and 63. Since the flip flop iscontinuously toggling in response to the T signal provided by the timingsignal generator 43, the AND gates 62 and 63 are alternately enabledthereby alternately providing the bias and the bias signals to theoptical bias apparatus 21 as indicated by the legend. Thus, whenever therate of rotation of the ring is less than the predetermined rate,alternating positive and negative optical bias is applied to the ringlaser by means of the optical bias apparatus 21 in a well known manner.As is well appreciated in the ring laser art, the optical bias may beapplied to prevent mode locking. As is furthermore understood in theringlaser art, the applied bias may be alternated between positive andnegative polarities to reduce drift in the rotational data provided bythe ring laser 20. Whenever the rate of rotation of the ring is equal toor greater than the predetermined rate, which is selected just beyondthe mode locking region illustrated in FIG. 1, the binary ZERO signalprovided by the inverter 64 disables both the AND gates 62 and 63thereby de-energizing the optical bias apparatus 21. Thus, in summary,whenever the rate of rotation of the ring is less than the predeterminedrate, alternating optical bias is applied to the ring to prevent modelocking and to decrease drift in the system, and whenever the rate ofrotation of the ring is equal to or greater than the predetermined rateand hence beyond the mode locking region of the ring lasercharacteristic, the optical bias is removed from the ring.

As previously described, the laser polarity selector 26 provides asignal representative of the polarity of the pulses of the laser pulsesequence. Whenever the rate of rotation of the ring is less than thepredetermined rate, the bias on signal from the inverter 64 of the biascontrol circuit 30 provides an enabling signal to the AND gate 27.

When, for example, negative bias is applied to the ring, the bias signalfrom the AND gate 63 of the bias control circuit 30 provides a binaryONE signal to the AND gate 27 of the laser polarity selector 26.Therefore, when the rate of rotation of the ring is less than thepredetermined rate and the applied bias is negative, the AND gate27provides a binary ONE signal via the OR gate 29 which signal isrepresentative of the negative polarity of the applied bias. When,however, at the low rates of rotation of the ring, the applied bias ispositive, the ANDgate 63 of the bias control circuit 30 is disabledthereby providing a binary ZERO signal to the AND gate 27. of the laserpolarity selector 26. Thus at the low rates of rotation of the ring andwhenever positive bias is applied, thereto, the AND gate 27 provides abinary ZERO. signal via theOR gate 29,which.signal is representative ofthe positive polarity of the "applied bias.

, Whenever the rate of rotation of the ring is equal to or greater thanthe predetermined rate, the bias on signal disables the AND gate 27 andthe bias off signal provides an enabling input to the AND gate 28. TheAND gate 28 provides the signal representativeof the polarity of thelaser pulses in accordance with the signal provided by the rate detector31 at the high rates of rotation of the ring in a manner to be explainedwith respect to the operation of the rate detector 31.

As previously described, the bias control circuit 30 provides biascontrol signals to the bias compensation and polarity selection circuits36. The bias compensation and polarity selection circuits 36 aregenerally comprised of the Y-registers 38, 39 and 40; the arithmeticunit 41; and the R-register 47 which components together form aconventional integrator circuit of the digital differential analyzertype disclosed in the reference previously cited. The Y-registers 38, 39and 40 are time shared by the arithmetic unit 41 in a conventionalmanner.

With the dx-input to the arithmetic unit 41 permanently connected to asource of positive voltage, which voltage is representative of a binaryONE signal, the fixed binary numbers selectively provided by the Y-registers 38, 39 and 40 via the OR gate 46 are continuously accumulatedin the R-register 47 by the arithmetic unit 41. Thus, the arithmeticunit 41 continuously provides a compensation pulse sequence at thedz-output thereof on the conductor 37 in the well known manner of anintegrator of the digital differential analyzer type. The compensationpulse sequence thereby provided has a pulse repetition frequencyproportional to the magnitudes of the respective binary numbers storedin the registers 38, 39 and 40.

At the low rates of rotation of the ring, the bias on signal from thebias control circuit 30 provides, an enabling signal to the AND gates 44and 45 and the interval 1 signal from the timing signal generator 43provides a timing signal thereto. The interval 1 signal may be ,aconventional timing signal for gating the binary numbers stored in theY-registers 39 and 40 through the AND gates 44 and 45, respectively,during a selected time interval. The alternately occurring bias signaland bias signal from the bias control circuit 30 also provide enablinginputs to the AND gates 44 and 45, respectively. Therefore, at the lowrates of rotation of the ring, the respective binary numbers stored inthe positive bias Y-register 39 and the negative bias Y-register 40 aretransmitted respectively through the AND gates 44 and 45, in accordancewith the interval 1 signal, to the OR gate 46 in an alternating mannerin response, respectively, to the alternately occurring bias and biassignals. The OR gate 46, in turn, transmits these numbers to the Y-inputof the arithmetic unit 41.

Hence, the registers 39 and 40 provide the respective numbers storedtherein, in a conventional manner, to the arithmetic unit 41 inaccordance with the control signals provided by the bias control circuit30 and the timing signals provided by the timing signal generator 43.For example, when positive bias is applied to the ring laser 20 at thelow rates of rotation thereof, the binary number stored in the positivebias Y-register 39, which number is representative of the magnitude ofthe applied positive bias, is transmitted to the Y-input of thearithmetic unit 41 via the AND gate 44 and the OR gate 46 in accordancewith the interval 1 signal. Since the dx-input of the arithmetic unit 41has a binary ONE signal permanently applied thereto, the positive biasbinary number in the Y-register 39 is repeatedly accumulated in theR-register 47. Thus, a compensation pulse sequence is provided on theconductor 37 by the arithmetic unit 41 whose pulse repetition frequencyis representative of the magnitude of the rate of the artificialrotation induced in the ring laser 20 by the positive optical biasapplied by the optical bias apparatus 21. In a similar manner, thenegative bias Y number stored in the Y-register 40 is selected toprovide a compensation pulse sequence on the conductor 37 whose pulserepetition frequency is representative of the magnitude of the rate ofartificial rotation induced in the ring laser 20 by the negative biasapplied by the optical bias apparatus 21.

A signal representative of the polarity of the compensation pulsesprovided on the conductor 37, is pro vided by the sz output of thearithmetic unit 41 on the conductor 56 in the conventional manner of adigital differential analyzer integrator of the type utilized in thebias compensation and polarity selection circuits 36 of the presentinvention. The compensation polarity signal on the conductor 56 isprovided in response to the sx-polarity input to the arithmetic unit 41.When the applied bias is positive, for example, the binary ONE outputfrom the AND gate 62 of the bias control circuit 30 enables the AND gate53 of the bias compensation and polarity selection circuits 36 therebyproviding a binary ONE signal, which is representative of a negativepolarity, to the sx-input of the arithmetic unit 41 via the OR gate 55.In a similar manner, when negative bias is applied to the ring laser 20,the binary ZERO signal provided by the AND gate 62 disables the AND gate53 thereby providing a binary ZERO signal to the sx-input of thearithmetic unit 41 which signal is representative of a positivepolarity. Thus a polarity opposite to that of the applied bias isselected for the optical bias compensation pulses in accordance with theteachings of the present invention. The AND gate 53 is also enabled inaccordance with the interval 1 timing signal thereby providing therespective polarity signals associated with the positive and negativeoptical bias -binary numbers stored respectively in the registers 39 and40 in.the sx-input of the arithmetic unit 41. The

arithmetic unit 41, therefore, in a conventional manner, adds the binarynumber applied to the Y-input thereof to the number stored in theR-register 47 or subtracts the number applied to the Y-input thereoffrom the number stored in the R-register 47 in accordance with thesx-input signal being in the binary ZERO state or the binary ONE state,respectively.

As previously explained, the instrument bias Y-register 38 provides abinary number representative of the instrument zero offset of theringlaser characteristic illustrated in FIG. 1. In a manner similar tothat described with respect to the optical bias, the instrument biasbinary number is accumulated in the R-register 47 by the arithmetic unit41 in accordance with the interval 2 signal provided by the timingsignal generator 43, thereby contributing to the compensation pulsesequence provided by the arithmetic unit 41 on the conductor 37. Sincethe instrument zero offset has a magnitude dependent upon the particularring laser selected for a particular mechanization of the presentinvention, the magnitude of the instrument bias binary number stored inthe Y-register 38 may be fixed in accordance therewith. Similarly, sincethe polarity of the instrument zero offset may be positive or negativein accordance with the particular ring laser selected, the polarity ofthe instrument bias compensation pulses may accordingly be set by theswitch 52. If the instrument zero offset is negative, for example, theswitch 52 may be set to the minus volts position, as indicated by thelegend, thereby disabling the AND gate 54 thus providing a binary ZEROsignal to the sx-input of the arithmetic unit 41 via the OR gate 55. Ina similar manner, a binary ONE signal associated with a positiveinstrument zero offset may be applied to the sx-input of the arithmeticunit 41 by setting the switch 52 to the positive volts position. Thus apolarity opposite to that of the instrument zero offset is selected forthe instrument compensation pulses in accordance with the teachings ofthe present invention. The AND gate 54 is also enabled in accordancewith the interval 2 timing signal thereby providing the selectedpolarity signal associated with the instrument bias binary number storedin the register 38.

It may be appreciated that when the rate of rotation of the ring isequal to or greater than the aforementioned predetermined rate, thesignal provided by the inverter 64 of the bias control circuit 30disables the AND gates 44 and 45 thereby discontinuing the generation ofthe optical bias compensation pulses on the conductor 37. It mayfurthermore be appreciated that the instrument zero offset is a fixedand undesired characteristic of a particular ring laser utilized toinstrument the system of the present invention. Therefore, during boththe high and the low rates of rotation of the ring the instrument biasY-register 38 provides the instrument bias binary number to thearithmetic unit 41 which continuously accumulates this number in theR-register 47 in accordance with the interval 2 timing signal and thepreset position of the switch 52. Therefore, the instrument biascompensation pulses are provided on the conductor 37 irrespective of themagnitude of the rate of rotation of the ring and the instrument biascompensation polarity signal associated therewith is provided on theconductor 56.

It may furthermore be appreciated that because of the alternatingcharacteristic of the bias and the bias control signals and because ofthe non-overlapping characteristic of the interval 1 and the interval 2timing signals, binary numbers from the Y-registers 38, 39 and 40 willnever simultaneously be applied to the arithmetic unit 41 thusprecluding erroneous applications of the Y-binary numbers thereto.

The reason for utilizing separate positive and negative bias Y-registers39 and 40 will now be explained. It is desired when optical bias isapplied to the ring laser 20 by the optical bias apparatus 21, that themagnitude of the current flow through the optical bias apparatus 21 bemaintained constant irrespective of the polarity of the bias applied.Constant bias current is desirable in ring laser systems because theoptical bias apparatus 21 is usually located internal to the temperaturesensitive optical cavity of the ring laser 20. Temperature gradients,which may be caused by the differences in the magnitude of current flowthrough the optical bias apparatus 21, may seriously distort thecritical optical dimensions of the cavity thus introducing errors.Maintaining the magnitude of the current flow constant, however,introduces an additional problem. Because of asymmetries inherent inoptical biasing apparatus, the applied positive optical bias may differfrom the applied negative optical bias for energizing currents of thesame magnitude. Therefore, positive and negative Y- binary numbers thatare different with respect to each other are required in accordance withthe different positive and negative optical bias provided by the opticalbias apparatus 21 in response to the current flow of constant magnitude.

As previously discussed, the laser pulse sequence, the laser pulsesequence polarity signal, the compensation pulse sequence and thecompensation pulse sequence polarity signal provide inputs to the pulsesequence combining circuit 66. The pulse sequence combining circuit 66provides a signal on the conductor 67 representative of singly occurringlaser or compensation pulses and provides a signal on the conductor 68representative of the polarity associated therewith. The pulse sequencecombining circuit 66 furthermore provides a signal on the conductor 67representative of one pulse of simultaneously occurring laser andcompensation pulses having the same polarity with respect to eachotherand provides a signal on the conductor 68 representative of thepolarity thereof. The pulse sequence combining circuit 66 stores theother pulse of the pair of simultaneously occurring laser andcompensation pulses with its associated polarity signal and thereaftertransmits the stored pulse and the stored polarity signal on theconductors 67 and 68 respectively. Whenever two simultaneously occurringlaser and compensation pulses have opposite polarities with respect toeach other, the pulses are cancelled and a signal is not transmitted onthe conductor 67.

Whenever a single laser pulse or a single compensation pulse occurs, theAND gates 86 and 88 are respectively enabled. The enabled AND gate 86 orthe enabled AND gate 88 may provide a binary ONE signal on the conductor67 via the OR gates 73 and 74. When, for example, a single positivelaser pulse occurs, the binary ZERO polarity signal from the laserpolarity selector 26 disables the AND gate 90 thereby providing a binaryZERO signal on the conductor 68 via the OR gates 91 and 85 and the ANDgate 92. This binary ZERO signal is representative of the positivepolarity of the laser pulse. When, however, the polarity of the singlyoccurring laser pulse is negative, the binary ONE polarity signal fromthe laser polarity selector 26 enables the AND gate 90 thereby providinga binary ONE signal on the conductor 68, which signal is representativeof the negative polarity of the laser pulse. In a similar mannerwhenever a single bias compensation pulse occurs, the compensationpolarity signal on the conductor 56 disables or enables the AND gate 98,in accordance with the pulse polarity being positive or explained, theOR gate 77 is also enabled, which in turn negative, respectively,thereby providing a binary- ZERO or a binary ONE signal respectively onthe conductor 68.

Whenever a laser pulse and a bias compensation pulse occursimultaneously with respect to each other and have the same polaritywith respect to each other, the AND gate 69 or the AND gate 72 isenabled when the associated polarity is positive or negativerespectively. When either the AND gate 69 or the AND gate 72 is enabled,a binary ONE signal is provided on the conductor 67 via the OR gates 73and 74 which signal is representative of one pulse of the pair ofsimultaneously occurring pulses. If the simultaneously occurring pulsesare negative, the binary ONE signal provided by the AND gate 72 istransmitted to the conductor 68 via the OR gates 85 and 91 and the ANDgate 92.'This signal, on the conductor 68, is representative of thenegative polarity. If, however, the two simultaneously occurringpulses'are positive, the binary ZERO signal from the AND gate 72 issimilarly transmitted to the conductor 68 via the OR gates 85 and 91 andthe AND gate 92.

Whenever the two simultaneously occurring pulses have the same polaritywith respect to each other, and either the AND gates 69 or 72 is enabledas previously sets the flip flop 78 to the 0 state in response to the tsignal on the T input thereof. Thus the flip flop 78 is causedeffectively to store the other pulse of the pair of simultaneouslyoccurring pulses. If the pair of simultaneously occurring pulses ispositive, the flip flop 79 is set to the Q state, and if the pair ofsimultaneously occurring pulses is negative, the flip flop 79 is set tothe 1 state. Thus the flip flop 79 is caused to store the polarity ofthe other pulse of the pair of simultaneously occurring pulses.

When the first pulse of the pair of simultaneously occurring pulses isbeing transmitted through the OR gate 73 to the conductor 67, the ORgate 73 provides an inhibiting signal to the AND gates 75 and 76 via theinverter 80. This inhibiting signal prevents the pulse stored in theflip flop 78 from being transmitted through the AND gate 75 and preventsthe polarity signal stored in the flip flop 79 from being transmittedthrough the AND gate 76 while the first pulse of the pair of pulsesexists on the conductor 67. During the time that this first pulseexists, the OR gate 73 provides.

an enabling signal to the AND gate 92 thereby permitting the polaritysignal associated with this first pulse to be transmitted therethroughto the conductor 68.

After the first pulse of the pair of simultaneously occurring pulses hasbeen transmitted through the OR gate 73 to the conductor 67, the OR gate73 enables the AND gates 75 and 76 and disables the AND gate 92. Thesecond pulse of the pair of pulses which second pulse is stored in theflip flop 78 is then transmitted through the AND gate 75 to theconductor 67 via the OR gate 74. This second pulse, transmitted throughthe AND gate 75, is also utilized to reset the flip flop'78 back to theO state. In a similar manner, the polarity signal associated with thissecond pulse, which polarity signal is stored in the flip flop 79, istransmitted through the AND gate 76 to the conductor 68 via the OR gate85. Since the AND gate 92 is, at this time, disabled by the signal fromthe OR gate 73, erroneous polarity signals are blocked from beingtransmitted to the OR gate and hence to the conductor 68.

It is to be appreciated that since the polarity of the optical biascompensation pulses is selected opposite to that of the bias applied tothe ring, in accordance with the teachings of the present invention,whenever a simultaneously occurring laser pulse and bias compensationpulse have the same polarity with respect to each other that the biascompensation pulse is an instrument bias compensation pulse.

As previously discussed, the pulse sequence combining circuit 66provides the combined pulse sequence on the conductor 67 and thecombined polarity signal associated therewith on the conductor 68. Theconductors 67 and 68 provide signals to-the dx and sx-inputsrespectively of the scaling integrator 93. The scaling integrator 93scales the combined pulse sequence in accordance with the combinedpolarity signal, in a conventional manner thereby providing a scaledcombined pulse sequence and an associated polarity signal at the dz andthe sz-outputs thereof respectively. The scaling factor may be chosen sothat the pulse sequence provided by the scaling integrator 93 to thefollowing sinecosine computation circuit 94 may be utilized directlythereby without requiring further scaling in the integrators associatedtherewith.

The scaling integrator 93 provides the scaled combined pulse sequenceand the polarity signal associated therewith to the rate detector 31 viathe dz and sz-outputs thereof respectively. The rate detector 31provides a signal on the conductor 97 to the bias control circuit 30which signal is representative of the condition wherein the magnitude ofthe rate of rotation of the ring equals or exceeds the aforementionedpredetermined magnitude. The rate detector 31 also provides a signal tothe laser polarity selector 26 which signal selects the polarity of thelaser pulse sequence at the high rates of rotation of the ring.

The timing signal T, periodically triggers the flip flop 104 at a ratewhich may, for convenience, be 122 Hertz. The binary informationprovided to the set and reset inputs of the flip flop 104 from the ANDgate 103 is thus periodically entered thereinto by the T, signal. The T,signal is also utilized to reset the counter 95 to a reference valuewhich may, for convenience, by zero, For reasons to be explained,conventional delaying means, not shown, are included in the counter 95for delaying the resetting thereof until the binary information has beenentered into the flip flop 104 by the T, signal.

Whenever the counter 95 is reset to zero by the T, signal and the flipflop 104 is in the O state, the AND gate 130 provides an enabling signalto the AND gates 131 and 132. The enabled AND gates 131 and 132 thenenter the polarity information provided by the szoutput of the scalingintegrator 93 into the flip flop 108 in response to the trigger pulsesapplied to the trigger input thereof. If the sz-signal is in the binaryZERO state, which is representative of a positive polarity, the flipflop 108 is set to the 6 state. If the sz-signal is in the binary ONEstate, which is representative of a negative polarity, the flip flop 108is set to the Q state.

The counter 95 is controlled to count up or down by a binary ZERO or abinary ONE signal respectively applied to the up-down control input 107,as previously explained. The up-down control signal is provided inaccordance with the polarity of the sz-signal from the scalingintegrator 93 and the state of the flip flop 108 via the gates 134, 135,136, and 137. These gates are interconnected so that the reversiblecounter 95 is not permitted to count down through zero as previouslyexplained. Instead, whenever the counter 95 attains a count of zero bycounting down from a larger number, the binary signal on the conductor107 is reversed, in a manner to be explained, so that the counter 95reverses its direction of count and commences counting up therefrom. Thecounter 95 is thus constrained from counting down through the numberzero for the reasons previously explained.

Considering now that the ring laser 20 is rotating at a rate whosemagnitude is less than the aforementioned predetermined magnitude, theT, signal continuously resets the counter 95 back to zero before it canattain the aforementioned predetermined count. Therefore, the AND gate103 remains continuously disabled thereby providing binary informationto the flip flop 104 which causes it to be continuously set to the Qstate in response to the T, signal. The flip flop 104,

therefore, provides a bias on signal, via the conductor 97, to the biascontrol circuit 30 and hence to the laser polarity selector circuit 26as previously explained.

The AND gate 130 is consequently periodically enabled therebyperiodically entering the sz polarity information from the scalingintegrator 93 into the flip flop 108. As previously explained, when thepolarity signal is positive, for example, the flip flop 108 is set tothe O state. In accordance with this condition, both the AND gates 134and 135 are disabled thereby providing a binary ZERO count-up controlsignal to the reversible counter 95. Similarly, when the polarity signalprovided by the scaling integrator 93 is negative, the flip flop 108 isset to the Q state thus again disabling both the AND gates 134 and 135and thus again providing a count-up signal to the counter 95. Thus itcan be seen that after the counter .95 is reset to zero, it will countup irrespective of the polarity signal provided by the scalingintegrator 93.

Considering still that the magnitude of the rate of rotation of the ringlaser 20 is less than the aforementioned predetermined magnitude, shouldthe polarity signal from the scaling integrator 93 reverse while thecounter 95 is counting up, the count-up control signal on the conductor107 will similarly reverse, hence causing the counter 95 to begincounting down. Should the counter attain a zero count when countingdown, the AND gate will be enabled hence causing the flip flop 108 tochange state in response to the reversed polarity signal therebyreversing the up-down control signal on the conductor 107 causing thecounter 95 to begin counting up again. Thus it can be seen that thereversible counter 95 will count in a numerical range equal to orgreater than zero and less than the aforementioned predetermined countat the low rates of rotation of the ring.

Consider now the condition wherein the magnitude of the rate of rotationof the ring equals or exceeds the aforementioned predeterminedmagnitude. The counter 95, which is periodically being reset to a countof zero by the T, signal, now attains the predetermined count during aresetting period thus enabling the AND gate 103. The enabled AND gate103 provides a disabling signal via the inverter 106 to the AND gate 96hence blocking transmission to the counter 95 of further pulses. Hencethe counter 95 stops counting upon attaining the predetermined count.The next occurring T, timing pulse sets the flip flop 104 to the Q stateand thereafter resets the reversible counter 95 back to zero. Theresetting of the counter 95 must be slightly delayed with respect to thesetting of the flip flop 104 so that the binary information provided bythe AND gate 103 is properly entered thereinto. The Q output of the flipflop 104 provides the high rate bias off signal on the conductor 97 tothe bias control circuit 30 and hence to the laser polarity selector 26.The 6 output of the flip flop 104 then disables the AND gate 130 thuspreventing the flip flop 108 from changing state in response to furtherpulses applied to its trigger input. The flip flop 108 is thus caused tostore a signal representative of the polarity signal provided by thescaling integrator 93 when the reversible counter 95 attains theaforementioned predetermined count. Hence the flip flop 108 provides thehigh rate laser polarity signal to the laser polarity selector 26.

The reversible counter 95, which is now reset to zero, reenables the ANDgate 103 which in turn re-enables the AND gate 96. Hence the counter 95again commences to count the pulses of the scaled combined pulsesequence from the scaling integrator 93 in an upward direction. If themagnitude of the rate of rotation of the ring still equals or exceedsthe predetermined magnitude, the described cycle is repeated and theflip flops 104 and 108 continue to provide the bias off signal and thehigh rate laser polarity signal respectively. If, however, the magnitudeof the rate of rotation of the ring has decreased to less than thepredetermined magnitude, the AND gate 103 will no longer be enabled andthe T signal will reset the flip flop 104 back .to the 6 state, henceagain providing the bias on signal on the conductor 97 as previouslyexplained.

As previously discussed, the scaling integrator 93 provides the scaledcombined pulse sequence and the polarity signal associated therewith tothe sine-cosine computation circuit 94 and the ratecomputation circuit113. As previously described, the sine-cosine computation circuit 94 isa conventional digital differential analyzer for providing the sine andthe cosine of the angular attitude of the ring laser 20 with respect toa reference position. Similarly, the rate computation circuit 113, aspreviously described, is a conventional digital differential analyzerfor providing a binary number representative of the sense and magnitudeof the rate of rotation of the ring laser 20.

The over-all operation of the computer illustrated in FIG. 2 will nowbeconsidered. The ring laser 20 provides three contributions to the laserpulse sequence. The first contribution consists of pulses resulting fromthe mechanical rotation of the ring about an axis normal thereto. Thesecond contribution consists of pulses resulting from the appliedoptical bias and the third contribution consists of pulses resultingfrom the instrument zero offset.

The bias compensation and polarity selection circuits 36 provide twocontributions to the bias compensation pulse sequence. The firstcontribution consists of pulses equal in number to the pulsescontributed to the laser pulse sequence by reason of the applied opticalbias and the second contribution consists of pulses equal in number tothe "pulses contributed to the laser pulse sequence by reason of theinstrument zero offset.

When the applied optical bias is positive, the laser polarity selectorcircuit 26 assigns a positive polarity to the pulses of the laser pulsesequence, which polarity is conveniently represented by a binary ZEROsignal in the'disclosed embodiment of the present invention. Similarly,the bias compensation and polarity selection circuits 36 assign anegative polarity to the pulses contributed to the bias compensationpulse sequence to compensate for the applied optical bias. This polarityis conveniently represented by a binary ONE signal. The laser and.optical bias compensation polarities are selected under control of thebias control circuit 30.

Conversely, when the applied optical bias is negative, a negativepolarity is assigned to the laser pulses and a positive polarity isassigned to the optical bias compensation pulses in the manner describedwith respect to the positive optical bias.

The polarity of the instrument bias compensation pulses is presetopposite to the fixed polarity of the instrument zero offset by theswitch 52.

The laser pulse sequence and the bias compensation pulse sequence areapplied to the pulse sequence combining circuit 66. As previouslydescribed, the pulse sequence combining circuit 66 transmits singlyoccurring laser or compensation pulses and the polarity signalsassociated therewith. The pulse sequence combining circuit 66furthermore transmits both pulses of each pair of simultaneouslyoccurring laser and compensation pulses having the same polarity withrespect to each other and transmitting the polarity signal associatedtherewith. Pairs of simultaneously occurring laser and compensationpulses having opposite polarities with respect to each other arecancelled by the pulse sequence combining circuit 66. Hence, the pulsesequence combining circuit 66 cancels a number of laser pulses resultingfrom the applied optical bias and a number of laser pulses resultingfrom the instrument zero offset and corresponding numbers of opticalbias compensation pulses and instrument compensation pulses,respectively. The remaining pulses provide the combined pulse sequenceon the conductor 67 and the associated combined polarity signalassociated therewith is provided on the conductor 68. It may hence beappreciated that the combined pulse sequence comprises intercurrentlaser and compensation pulses and that the combined polarity signalcomprises corresponding intercurrent positive and negative signals.

The combined pulse sequence is scaled and the scaled combined pulsesequence is applied to the sinecosine computation circuit 94 and to therate computation circuit 113 along with the associated combined polaritysignals. The sine-cosine computation circuit 94 and the rate computationcircuit 113 are conventional digital differential analyzers comprisingintegrator circuits of the type previously cited. The scaled combinedpulse sequence, as previously explained, comprises laser pulsesresulting from mechanical rotation of the ring, the applied optical biasand the instrument zero offset; the laser pulses having a selectedpolarity. The scaled combined pulse sequence further includes opticalbias compensation pulses having a polarity selected opposite to that ofthe laser pulses and instrument bias compensation pulses having a presetpolarity selected opposite to that of the instrument zero offset. Theintegrators of the digital differential analyzers, hence, integrate thepulses of the scaled combined pulse sequence in accordance with thepolarity signals associated therewith, thus providing data from whichthe effect of the applied optical bias and the instrument zero offsethave been removed. The data provided by the sine-cosine computationcircuit 94 and the rate computation circuit 113, therefore, arerespective of the magnitude and polarity of the mechanical rotation ofthe ring laser about its sensitive axis.

The scaledcombined pulse sequence and the polarity signals associatedtherewith are also applied to the rate detector 31. The reversiblecounter 95 of the rate detector 31 counts up when the pulse appliedthereto is of one polarity and counts down when the applied pulse I isof the other polarity. within the constraintof not counting down throughzero as previously described. Thus, the counter 95 provides a binarynumber representative of the number of laser pulses resulting from themechanical rotation of the ring that occur within the resettingintervalof the counter 95. The binary number thus provided isrepresentative of the magnitude of the rate of rotation of the ring. TheAND gate 103, therefore, detects when the magnitude of the rate ofrotation of the ring equals or exceeds the aforementioned predeterminedmagnitude thus providing the high rate signal on the conductor 97 to thebias control circuit 30.

At the high rates of rotation of the ring, the bias control circuit 30de-energizes the optical bias apparatus 21 and inhibits the optical biascompensation pulses from transmission to the pulse sequence combiningcircuit 66 in response to the signal on the lead 97. The flip flop 108of the rate detector 31 provides the laser polarity signal, via thelaser polarity selector 26, during the high rates of rotation of thering, as previously described.

At the low rates of rotation of the ring, the bias control circuit 30energizes the optical bias apparatus 21, enables the optical biascompensation pulses for transmission to the pulse sequence combiningcircuit 66 and selects the laser and compensation polarities via thelaser polarity selector 26 and the bias compensation and polarityselection circuits 36, respectively, as previously described. Thepolarity of the applied bias may be continuously alternated, at the lowrates of rotation, to reduce long-term drift errors in the manner wellknown in the ring laser art. The laser and compensation polarities maybe correspondingly alternated, thus continuously providing signals fromthe computer of the present invention representative of the magnitudeand the sense of the rate of rotation of the ring about its sensitiveaxis.

It may be appreciated that the computer of the present inventin mayprovide navigational data with respect to a vehicle in which the ringlaser 20 may be fixedly mounted. The sensitive axis of the ring may bealigned with one of the major axes of the vehicle, for example with thepitch axis of the craft. The sine-cosine computation circuit 94 maythen, for example, provide signals representative of the sine and thecosine of the pitch displacement of the craft with respect to areference position.

It may thus further be appreciated that the computer of the presentinvention is particularly suited to providing navigational data in athree-axis navigational system which may compute, for example, the basicdirection cosines of the vehicle navigating with respect to a referenceframe fixed in space. It will be appreciated that in the abovespecification the terms sx, sy, sz represent the polarities of therespective dx, dy, dz signals and may alternatively be designated as S8,, S, respectively.

While the invention has been described in its preferred embodiment, itis to be understood that the words which have been used are words ofdescription rather than limitation and that changes may be made withinthe purview of the appendedclaims without deabout an axisnormal theretoincluding a ring laser having contrarotating beams and biasing means forselectivelychanging the effective optical path length around said ringof one of said beams with respect to the other, said ring laserproviding a laser pulse sequence whose pulse repetition frequency isrepresentative of the difference in oscillation frequency between saidbeams:

laser polarity selection means for providing a first polarity signalrepresentative of a polarity associated with said laser pulse sequence,compensation means for providing a bias compensation pulse sequencewhose pulse repetition frequency is representative of the change in saideffective optical path length effected by said biasing means,compensation polarity selection means for providing a second polaritysignal representative of a polarity associated with said biascompensation pulse sequence and selected of opposite polarity to that ofsaid first polarity signal, and 7 pulse sequence combining meansresponsive to said laser pulse sequence, first polarity signal, biascompensation pulse sequence and second polarity signal for providing acombined pulse sequence and a combined polarity signal in accordancetherewith.

2. In the system recited in claim 1 in which said pulse sequencecombining means comprises means for inhibiting each said laser pulse andeach said bias compensation pulse that occur simultaneously with respectto each other and have opposite associated polarities with respect toeach other and transmitting each said laser pulse and each said biascompensation pulse that occur separately with respect to each otherthereby providing said combined pulse sequence'and for transmitting thepolarity signal associated with each said transmitted pulse therebyproviding said combined polarity signal.

3. In the system recited in claim 1 in which said laser polarityselection means includes means for selecting the polarity of said firstpolarity signal in accordance with the polarity of said bias.

4. In the system recited in claim 3 in which said compensation meansincludes means for selectively providing a plurality of biascompensation pulse sequences.

5. In the system recited in claim 4 further including bias control meansfor providing signals to said biasing means for alternately reversingsaid polarity of said bias.

6. In the system recited in claim 3 in which said compensation meansincludes means for selectively providing first and second biascompensation pulse sequences in accordance with said polarity of saidbias.

7. In the system recited in claim 6 further including bias control meansfor providing bias control signals;

said biasing means, said means for selecting the polarity of said firstpolarity signal in accordancev withthe polarity of said bias, said meansfor selectivelyproviding first and second bias compensation pulsesequences in accordance with said polarity of said bias and saidcompensation polarity selection means for controlling said polarity of'said bias being responsive to said control signals for selecting thepolarity of said first polarity signal, for selectively providing saidfirst and second bias compensation pulse sequences and for selecting thepolarity of said second polarity signal, respectively.

whose pulse repetition frequency is representative of the zero offset ofthe response curve of said ring laser, and

said compensation polarity selection means further includes instrumentcompensation polarity selection means for providing to said pulsesequence combining means a signal representative of a predeterminedinstrument compensation polarity associated with said instrumentcompensation pulse sequence.

10. In the system recited in claim 9 in which said compensation meanscomprises an integrator of the digital differential analyzer typewherein predetermined numbers stored in respective Y-registersassociatedwith said integrator are selectively accumulated in the R-.registerassociated therewith thereby providing respectively said first biascompensation pulse sequence, said second bias compensation pulsesequence and said instrument compensation pulse sequence.

11. In the system recited in claim 9 in which said pulse sequencecombining means comprises means for inhibiting each said laser pulse andeach said bias compensation pulse that occur simultaneously with respectto each other and have opposite associated polarities with respecttoeach other and transmitting each said laser pulse and each said biascompensation pulse that occur separately with respect to each otherthereby providing said combined pulse sequence and for transmitting thepolarity signal associated with each said transmitted pulse therebyproviding said combined polarity signal.

12. In the system recited in' claim -9 in which said pulse sequencecombining means further includes means responsive to said laser pulsesequence and to I said instrument compensation pulse sequence forinhibiting each said laser pulse and eachsaid instrument. compensationpulse that occur simultaneously with respect to each other and haveopposite associated polarities with respect to each other, meansresponsive to said laser pulse sequence and to said instrumentcompensation pulse sequence for transmitting one pulse of simultaneouslyoccurring laser and instrument compensation pulses having the sameassociated polarities with respect to each other thereby providing apulse of said combined pulse sequence,

means for storing the other pulse of said simultaneously occurring laserand instrument compensating pulses having the same associated polaritieswith respect to each other and for thereafter transmitting said otherpulse thereby providing apulse of said combined pulse sequence, and

means for storing the polarity signal associated with said other pulseand for transmitting said polarity signal associated therewithconcurrently with the transmission of said other pulse.

13. In the system recited in claim 1 further including first computationmeans coupled to said pulse sequence combining means and responsive tosaid combined pulse sequence and said combined polarity signal forproviding signals in accordance therewith representative of the sine andcosine of the angular displacement of said ring about said axis normalthereto, and

second computation means coupled to said pulse sequence combining meansand responsive to said combined pulse sequence and said combinedpolarity signal for providing a digital signal in accordance therewithrepresentative of the angular velocity of said ring about said axisnormal thereto. 14. In the system recited in claim 13 in which saidfirst and second computation means comprise integrator circuits of thedigital differential analyzer type.

15. In the system recited in claim 1 further including bias controlmeans for providing bias control signals to said biasing means forenergization and de-energization thereof.

16. In the system recited in claim 15 further including rate detectormeans responsive to said combined pulse sequence and said combinedpolarity signal for providing a de-energizing signal and a rate detectorpolarity signal whenever the magnitude of said rate of rotation exceedsa predetermined magnitude,

said rate detector polarity signal being representative of saiddirection of rotation of said ring about said axis normal thereto whenthe magnitude of said rate of rotation exceeds said predeterminedmagnitude, said bias control means being responsive to said deenergizingsignal for de-energizing said biasing means,

said-laser polarity selection means including means responsive to saidde-energizing signal and said rate detector polarity signal forproviding said first polarity signal in accordance with said ratedetector polarity signal, and

said compensation means being responsive to said de-energizing signalfor inhibiting said bias compensation pulse sequence from transmissionto said pulse sequence combining means.

17. In the system recited in claim 16 in which said rate detector meanscomprises a reversible pulse counter for counting the pulses of saidcombined pulse sequence selectively in an upward or downward directionin accordance with said combined polarity signal, means for periodicallyresetting said counter, means coupled to said counter for detecting apredetermined count to provide said de-energizing signal whenever saidcounter attains said predetermined count during said resetting period,and

storage means responsive to said combined polarity signal for storingthe polarity signal associated with the pulse of said combined pulsesequence that caused said counter to attain said predetermined countthereby providing said rate detector polarity signal.

18. In the system recited in claim 1 further including scaling meansresponsive to said combined pulse sequence and said combined polaritysignal for multiplying said combined pulse sequence in accordance withsaid combined polarity signal by the desired scale factor therebyproviding a signal representative of said rate and direction of rotationof said ring about said axis normal thereto.

19. In the system recited in claim 18 in which said scaling meanscomprises an integrator of the digital differential analyzer typewherein a predetermined binary number representative of the desiredscale factor is stored in the Y-register associated with saidintegrator.

20. In the system recited in claim 1 further including integrating meansresponsive to said combined pulse sequence and combined polarity signalfor integrating said combined pulse sequence in accordance with saidcombined polarity signal thereby providing a signal representative ofsaid rate and direction of rotation of said ring about said axis normalthereto.

21. In the system recited in claim 20 in which said integrating meansfurther includes first computation means for providing signalsrepresentative of the sine and the cosine of the angular displacement ofsaid ring about said axis normal thereto, and

second computation means for providing a digital signal representativeof the angular velocity of said ring about said axis normal thereto.

22. In the system recited in claim 21 in which said first and secondcomputation means comprise integrator circuits of the digitaldifferential analyzer type.

1. In a ring laser rotational rate sensor system for measuring the rateand direction of rotation of the ring about an axis normal theretoincluding a ring laser having contrarotating beams and biasing means forselectively changing the effective optical path length around said ringof one of said beams with respect to the other, said ring laserproviding a laser pulse sequence whose pulse repetition frequency isrepresentative of the difference in oscillation frequency between saidbeams: laser polarity selection means for providing a first polaritysignal representative of a polarity associated with said laser pulsesequence, compensation means for providing a bias compensation pulsesequence whose pulse repetition frequency is representative of thechange in said effective optical path length effected by said biasingmeans, compensation polarity selection means for providing a secondpolarity signal representative of a polarity associated with said biascompensation pulse sequence and selected of opposite polarity to that ofsaid first polarity signal, and pulse sequence combining meansresponsive to said laser pulse sequence, first polarity signal, biascompensation pulse sequence and second polarity signal for providing acombined pulse sequence and a combined polarity signal in accordancetherewith.
 1. In a ring laser rotational rate sensor system formeasuring the rate and direction of rotation of the ring about an axisnormal thereto including a ring laser having contrarotating beams andbiasing means for selectively changing the effective optical path lengtharound said ring of one of said beams with respect to the other, saidring laser providing a laser pulse sequence whose pulse repetitionfrequency is representative of the difference in oscillation frequencybetween said beams: laser polarity selection means for providing a firstpolarity signal representative of a polarity associated with said laserpulse sequence, compensation means for providing a bias compensationpulse sequence whose pulse repetition frequency is representative of thechange in said effective optical path length effected by said biasingmeans, compensation polarity selection means for providing a secondpolarity signal representative of a polarity associated with said biascompensation pulse sequence and selected of opposite polarity to that ofsaid first polarity signal, and pulse sequence combining meansresponsive to said laser pulse sequence, first polarity signal, biascompensation pulse sequence and second polarity signal for providing acombined pulse sequence and a combined polarity signal in accordancetherewith.
 2. In the system recited in claim 1 in which said pulsesequence combining means comprises means for inhibiting each said laserpulse and each said bias compensation pulse that occur simultaneouslywith respect to each other and have opposite associated polarities withrespect to each other and transmitting each said laser pulse and eachsaid bias compensation pulse that occur separately with respect to eachother thereby providing said combined pulse sequence and fortransmitting the polarity signal associated with each said transmittedpulse thereby providing said combined polarity signal.
 3. In the systemrecited in claim 1 in which said laser polarity selection means includesmeans for selecting the polarity of said first polarity signal inaccordance with the polarity of said bias.
 4. In the system recited inclaim 3 in which said compensation means includes means for selectivelyproviding a plurality of bias compensation pulse sequences.
 5. In thesystem recited in claim 4 further including bias control means forproviding signals to said biasing means for alternately reversing saidpolarity of said bias.
 6. In the system recited in claim 3 in which saidcompensation means includes means for selectively providing first andsecond bias compensation pulse sequences in accordance with saidpolarity of said bias.
 7. In the system recited in claim 6 furtherincluding bias control means for providing bias control signals; saidbiasing means, said means for selecting the polarity of said firstpolarity signal in accordance with the polarity of said bias, said meansfor selectively providing first and second bias compensation pulsesequences in accordance with said polarity of said bias and saidcompensation polarity selection means for controlling said polarity ofsaid bias being responsive to said control signals for selecting thepolarity of said first polarity signal, for selectively providing saidfirst and second bias compensation pulse sequences and for selecting thepolarity of said second polarity signal, respectively.
 8. In the systemrecited in claim 7 in which said bias control means further includesmeans for alternately reversing said bias control signals to alternatelyreverse said polarity of said bias, alternately reverse said polaritiesof first and second polarity signals, and alternately select said firstand second bias compensation pulse sequences.
 9. In the system recitedin claim 6 in which said compensation means further includes means forproviding to said pulse sequence combining means and instrumentcompensation pulse sequence whose pulse repetition frequency isrepresentative of the zero offset of the response curve of said ringlaser, and said compensation polarity selection means further includesinstrument compensation polarity selection means for providing to saidpulse sequence combining means a signal representative of apredetermined instrument compensation polarity associated with saidinstrument compensation pulse sequence.
 10. In the system recited inclaim 9 in which said compensation means comprises an integrator of thedigital differential analyzer type wherein predetermined numbers storedin respective Y-registers associated with said integrator areselectively accumulated in the R-register associated therewith therebyproviding respectively said first bias compensation pulse sequence, saidsecond bias compensation pulse sequence and said instrument compensationpulse sequence.
 11. In the system recited in claim 9 in which said pulsesequence combining means comprises means for inhibiting each said laserpulse and each said bias compensation pulse that occur simultaneouslywith respect to each other and have opposite associated polarities withrespect to each other and transmitting each said laser pulse and eachsaid bias compensation pulse that occur separately with respect to eachother thereby providing said combined pulse sequence and fortransmitting the polarity signal associated with each said transmittedpulse thereby providing said combined polarity signal.
 12. In the systemrecited iN claim 9 in which said pulse sequence combining means furtherincludes means responsive to said laser pulse sequence and to saidinstrument compensation pulse sequence for inhibiting each said laserpulse and each said instrument compensation pulse that occursimultaneously with respect to each other and have opposite associatedpolarities with respect to each other, means responsive to said laserpulse sequence and to said instrument compensation pulse sequence fortransmitting one pulse of simultaneously occurring laser and instrumentcompensation pulses having the same associated polarities with respectto each other thereby providing a pulse of said combined pulse sequence,means for storing the other pulse of said simultaneously occurring laserand instrument compensating pulses having the same associated polaritieswith respect to each other and for thereafter transmitting said otherpulse thereby providing a pulse of said combined pulse sequence, andmeans for storing the polarity signal associated with said other pulseand for transmitting said polarity signal associated therewithconcurrently with the transmission of said other pulse.
 13. In thesystem recited in claim 1 further including first computation meanscoupled to said pulse sequence combining means and responsive to saidcombined pulse sequence and said combined polarity signal for providingsignals in accordance therewith representative of the sine and cosine ofthe angular displacement of said ring about said axis normal thereto,and second computation means coupled to said pulse sequence combiningmeans and responsive to said combined pulse sequence and said combinedpolarity signal for providing a digital signal in accordance therewithrepresentative of the angular velocity of said ring about said axisnormal thereto.
 14. In the system recited in claim 13 in which saidfirst and second computation means comprise integrator circuits of thedigital differential analyzer type.
 15. In the system recited in claim 1further including bias control means for providing bias control signalsto said biasing means for energization and de-energization thereof. 16.In the system recited in claim 15 further including rate detector meansresponsive to said combined pulse sequence and said combined polaritysignal for providing a de-energizing signal and a rate detector polaritysignal whenever the magnitude of said rate of rotation exceeds apredetermined magnitude, said rate detector polarity signal beingrepresentative of said direction of rotation of said ring about saidaxis normal thereto when the magnitude of said rate of rotation exceedssaid predetermined magnitude, said bias control means being responsiveto said de-energizing signal for de-energizing said biasing means, saidlaser polarity selection means including means responsive to saidde-energizing signal and said rate detector polarity signal forproviding said first polarity signal in accordance with said ratedetector polarity signal, and said compensation means being responsiveto said de-energizing signal for inhibiting said bias compensation pulsesequence from transmission to said pulse sequence combining means. 17.In the system recited in claim 16 in which said rate detector meanscomprises a reversible pulse counter for counting the pulses of saidcombined pulse sequence selectively in an upward or downward directionin accordance with said combined polarity signal, means for periodicallyresetting said counter, means coupled to said counter for detecting apredetermined count to provide said de-energizing signal whenever saidcounter attains said predetermined count during said resetting period,and storage means responsive to said combined polarity signal forstoring the polarity signal associated with the pulse of said combinedpulse sequence that caused said counter to attain said predeterminedcount thereby providing said rate detector polarity signal.
 18. IN thesystem recited in claim 1 further including scaling means responsive tosaid combined pulse sequence and said combined polarity signal formultiplying said combined pulse sequence in accordance with saidcombined polarity signal by the desired scale factor thereby providing asignal representative of said rate and direction of rotation of saidring about said axis normal thereto.
 19. In the system recited in claim18 in which said scaling means comprises an integrator of the digitaldifferential analyzer type wherein a predetermined binary numberrepresentative of the desired scale factor is stored in the Y-registerassociated with said integrator.
 20. In the system recited in claim 1further including integrating means responsive to said combined pulsesequence and combined polarity signal for integrating said combinedpulse sequence in accordance with said combined polarity signal therebyproviding a signal representative of said rate and direction of rotationof said ring about said axis normal thereto.
 21. In the system recitedin claim 20 in which said integrating means further includes firstcomputation means for providing signals representative of the sine andthe cosine of the angular displacement of said ring about said axisnormal thereto, and second computation means for providing a digitalsignal representative of the angular velocity of said ring about saidaxis normal thereto.